3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
Clock Duty Cycle Stabilizer
Internal Reference with Support for External Reference
No External Decoupling Required for References
Programmable Output Clock Position and Drive Strength to Ease Data Capture
3.3 V Analog and 1.8 V to 3.3 V Digital Supply
32-QFN Package (5 mm × 5 mm)
Pin Compatible 12-Bit Family (ADS612X)
APPLICATIONS
Wireless Communications Infrastructure
Software Defined Radio
Power Amplifier Linearization
802.16d/e
Test and Measurement Instrumentation
High Definition Video
Medical Imaging
Radar Systems
ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies.
It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.
The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as ? controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability.
The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up.
ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.
The devices are specified over the industrial temperature range (-40°C to 85°C).