? AEC-Q10x qualified ? Core – Max fCPU： 24 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark ? Memories – Program memory： 32 to 128 Kbyte Flash program; data retention 20 years at 55 °C – Data memory： up to 2 Kbyte true data EEPROM; endurance 300 kcycle – RAM： 6 Kbyte ? Clock management – Low-power crystal resonator oscillator with external clock input – Internal， user-trimmable 16 MHz RC and low-power 128 kHz RC oscillators – Clock security system with clock monitor ? Reset and supply management – Wait/auto-wakeup/Halt low-power modes with user definable clock gating – Low consumption power-on and powerdown reset ? Interrupt management – Nested interrupt controller with 32 vectors – Up to 37 external interrupts on 5 vectors