1.1.1 Purpose This document describes the features， architecture， and programming model of NXP‘s MWCT1xxx series of microcontrollers. 1.1.2 Audience This document is primarily for system architects and software application developers who are using or considering using this chip in a system

　　The WCT1xxx microcontroller is a member of the 32-bit 56800EX core devices. It combines， on a single chip， the processing power of a 32-bit DSP and the functionality of a microcontroller with a flexible set of peripherals. Due to its cost-effectiveness， configuration flexibility， and compact program code， WCT1xxx is well-suited for many consumer and automotive wireless charging. The 56800EX core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel， allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient， compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. Additionally， memory resource protection （MRP） is provided to protect supervisor programs and resources from user programs. The on-chip flash memory and RAM can be mapped into both the program and data memory spaces. Two data operands can be accessed from the on-chip data RAM per instruction cycle.