As we approach nanometer design and beyond, the completeness of design verifications
related to physical design has become a key factor to working silicon in functionality as well
as performance. Besides the required white box, black box test suites which check for
functionality of the design, parasitics extraction is a must to reflect the actual timing delay of
signal routes. Signals crosstalk is a well-known issue which affects signal integrity. Special
attention should also be paid to address IR drop on the power supplies which directly degrade
the transistor performance.
As we are planning on the design & verification flow for the next generation SOC, should
we focus more on static or dynamic or both? This paper will attempt to address some of the
newer issues in both approaches.