The verification task of today’s multi-million gates
designs has become the primary bottleneck in the design
flow. Industry estimates are that functional verification
takes approximately 70% of the total effort on a project.
Rising gate count combine with greater design complexity
has lead to much longer verification times. Time-to-market
schedules are much harder to meet while project costs
increase. According to a survey conducted by Collett
International Research Inc. in 2002 [9], 60% of all tapeouts,
that requires silicon re-spin, contained logic or functional
flaws. Among those faulty integrated circuits, 82% had
design errors. Incorrect or incomplete specifications,
corner cases simply not covered during verification or
changes in design specifications are a few causes of these
flaws.
New verification techniques and methodologies are
required to cut verification time and improve the quality of
verification. Hopefully, hardware verification languages
(HVL) come to the rescue, raising the testbench at a higher
abstraction level. With specific verification syntax and
faster simulation speed, HVLs improve performance and
quality compared to RTL testbenches, thus reducing the
time spent in verification.
In this work we focus our efforts toward the
verification of digital signal processing (DSP) applications.
Most signal processing designs begin with algorithmic
modeling in the MATLAB and Simulink environment.
Therefore, we believe that hardware verification could be
significantly improved and accelerated by reusing these
high level golden references models.