The PX1011A/PX1012A is a high-performance, low-power, single-lane PCI Express
electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and
signaling. The PX1011A/1012A PCI Express PHY is compliant to the PCI Express Base
Speci?cation, Rev. 1.0a, and Rev. 1.1. The PX1011A/1012A includes features such as
clock and data recovery (CDR), data serialization and de-serialization, 8b/10b encoding,
analog buffers, elastic buffer and receiver detection, and provides superior performance to
the Media Access Control (MAC) layer devices.
The PX1011A/1012A is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface.
Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE)
speci?cation, enhanced and adapted for off-chip applications with the introduction of a
source synchronous clock for transmit and receive data. The 8-bit data interface operates
at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O
interfaces available in FPGA products.
The PX1011A/1012A PCI Express PHY supports advanced power management
functions. The PX1011AI/PX1012AI is for the industrial temperature range (?40 °C to
+85 °C).

2.1 PCI Express interface
n Compliant to PCI Express Base Speci?cation 1.1
n Single PCI Express 2.5 Gbit/s lane
n Data and clock recovery from serial stream
n Serializer and De-serializer (SerDes)
n Receiver detection
n 8b/10b coding and decoding, elastic buffer and word alignment
n Supports loopback
n Supports direct disparity control for use in transmitting compliance pattern
n Supports lane polarity inversion
n Low jitter and Bit Error Rate (BER)
2.2 PHY/MAC interface
n Based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE)
n Adapted for off-chip with additional synchronous clock signals (PXPIPE)
n 8-bit parallel data interface for transmit and receive at 250 MHz
n 2.5 V SSTL_2 class I signaling