資料介紹
The MAX1121 is a monolithic 8-bit, 250Msps analog-todigital
converter (ADC) optimized for outstanding
dynamic performance at high IF frequencies up to
500MHz. The product operates with conversion rates of
up to 250Msps while consuming only 477mW.
At 250Msps and an input frequency of 100MHz, the
MAX1121 achieves a spurious-free dynamic range
(SFDR) of 68dBc. Its excellent signal-to-noise ratio
(SNR) of 48.9dB at 10MHz remains flat (within 0.5dB)
for input tones up to 500MHz. This makes the MAX1121
ideal for wideband applications such as digital predistortion
in cellular base-station transceiver systems.
The MAX1121 requires a single 1.8V supply. The analog
input is designed for either differential or singleended
operation and can be AC- or DC-coupled. The
ADC also features a selectable on-chip divide-by-2
clock circuit, which allows the user to apply clock frequencies
as high as 500MHz. This helps to reduce the
phase noise of the input clock source. A differential
LVDS sampling clock is recommended for best performance.
The converter’s digital outputs are LVDS compatible,
and the data format can be selected to be
either two’s complement or offset binary.
The MAX1121 is available in a 68-pin QFN with
exposed pad (EP) and is specified over the industrial
(-40°C to +85°C) temperature range.
For pin-compatible, higher resolution versions of the
MAX1121, refer to the MAX1122 (170Msps), the
MAX1123 (210Msps), and the MAX1124 (250Msps)
data sheets.
converter (ADC) optimized for outstanding
dynamic performance at high IF frequencies up to
500MHz. The product operates with conversion rates of
up to 250Msps while consuming only 477mW.
At 250Msps and an input frequency of 100MHz, the
MAX1121 achieves a spurious-free dynamic range
(SFDR) of 68dBc. Its excellent signal-to-noise ratio
(SNR) of 48.9dB at 10MHz remains flat (within 0.5dB)
for input tones up to 500MHz. This makes the MAX1121
ideal for wideband applications such as digital predistortion
in cellular base-station transceiver systems.
The MAX1121 requires a single 1.8V supply. The analog
input is designed for either differential or singleended
operation and can be AC- or DC-coupled. The
ADC also features a selectable on-chip divide-by-2
clock circuit, which allows the user to apply clock frequencies
as high as 500MHz. This helps to reduce the
phase noise of the input clock source. A differential
LVDS sampling clock is recommended for best performance.
The converter’s digital outputs are LVDS compatible,
and the data format can be selected to be
either two’s complement or offset binary.
The MAX1121 is available in a 68-pin QFN with
exposed pad (EP) and is specified over the industrial
(-40°C to +85°C) temperature range.
For pin-compatible, higher resolution versions of the
MAX1121, refer to the MAX1122 (170Msps), the
MAX1123 (210Msps), and the MAX1124 (250Msps)
data sheets.
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