The SN65LVDS305 serializer device converts 27 parallel data inputs to one sub-low-voltage differential signaling (SubLVDS) serial output. It loads a shift register with 24 pixel bits and 3 control bits from the parallel CMOS input interface. In addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. Each word is latched into the device by the pixel clock (PCLK). The parity bit (odd parity) allows a receiver to detect single bit errors. The serial shift register is uploaded at 30 times the pixel-clock data rate. A copy of the pixel clock is output on a separate differential output.

FPC cabling typically interconnects the SN65LVDS305 with the display. Compared to parallel signaling, the SN65LVDS305 outputs reduce the EMI of the interconnect by over 20 dB.