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基于FPGA與DSP的雷達(dá)高速數(shù)據(jù)采集系統(tǒng)

1692742 2010-12-11 | rar | 559 | 次下載 | 5積分

資料介紹

?激光雷達(dá)的發(fā)射波及回波信號經(jīng)光電器件轉(zhuǎn)換形成的電信號具有脈寬窄，幅度低，背景噪聲大等特點(diǎn)，對其進(jìn)行低速數(shù)據(jù)采集存在數(shù)據(jù)精度不高等問題。同時，A/D轉(zhuǎn)換器與數(shù)字信號處理器直接連接會導(dǎo)致數(shù)據(jù)傳輸不及時，影響系統(tǒng)可靠性、實(shí)時性。針對激光雷達(dá)回?fù)苄盘?，提出基?a target='_blank' class='arckwlink_none'>FPGA與DSP的高速數(shù)據(jù)采集系統(tǒng)，利用FPGA內(nèi)部的異步FIFO和DCM實(shí)現(xiàn)A/D轉(zhuǎn)換器與DSP的高速外部存儲接口（EMIF）之間的數(shù)據(jù)傳輸。介紹了ADC外圍電路、工作時序以及DSP的EMIF的設(shè)置參數(shù)，并對異步FIFO數(shù)據(jù)讀寫進(jìn)行仿真，結(jié)合硬件結(jié)構(gòu)詳細(xì)地分析設(shè)計應(yīng)注意的問題。系統(tǒng)采樣率為30 MHz，采樣精度為12位。

Abstract:: ?Laser radar echo signal converted by photoelectric conversion has the characteristics of narrow pulse width, low amplitude and high background noise. The accuracy of the signal would not be high when using low speed data acquisition. Meanwhile, connecting the digital signal processor to A/D converter directly would lead to the not-timely data transfer, and affect system’s reliability and real-time. This paper proposed a high-speed data acquisition system based on FPGA and DSP aiming at the laser radar echo signal. The data transfer between A/D converter and the high-speed external memory interface （EMIF） of DSP was achieved by using FPGA internal asynchronous FIFO and DCM. The peripheral circuit, timing sequence of ADC and the parameters of EMIF were described, and the timing of writing and reading FIFO was simulated. The key points of the hardware design were also proposed. The sample rate of system is 30MHz, and resolution is 12bits.