1. Introduction This document describes the operation of the IP00C732 Quad-Scaler device from i-Chips Technology， Inc. and the types of applications it can be used for. It also presents examples of register settings and parameter calculations used in those applications. All examples in this document are intended for reference only， and are included to assist users in their design process. 1.1 Document Conventions ? The word “Scaler” can be used in the text to refer to the IP00C732 device. ? To refer to specific registers， the form “Bn_RegisterName （address）” is used， where “n” is the bank number. Unless otherwise specified， the register names and addresses apply to all the devices mentioned above. 1.2 CPU Interface and Register Access The 4-line serial access is in 2 8-bit units （1-bit R/W flag + 7-bit offset address + 8-bit data）。 Writing must be ordered from MSB to LSB. Some microprocessors may also require processing to invert bit strings in 8-bit units. CPU access can also be done in parallel mode， with the 8-bit CPU port. If the OSD feature is used， the CPU interface must be in parallel mode to load the OSD data in the memory. Setting of the register bank is done by writing the bank number at address 00h （RGBNK register）