The CY7C10612DV33 is a high performance CMOS Static RAM organized as 1，048，576 words by 16 bits. To write to the device， take Chip Enables （CE） and Write Enable （WE） input LOW. If Byte Low Enable （BLE） is LOW， then data from I/O pins （I/O0 through I/O7）， is written into the location specified on the address pins （A0 through A19）。 If Byte High Enable （BHE） is LOW， then data from I/O pins （I/O8 through I/O15） is written into the location specified on the address pins （A0 through A19）。 To read from the device， take Chip Enables （CE） and Output Enable （OE） LOW while forcing the Write Enable （WE） HIGH. If Byte Low Enable （BLE） is LOW， then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable （BHE） is LOW， then data from memory appears on I/O8 to I/O15. See Truth Table on page 10 for a complete description of Read and Write modes. The input or output pins （I/O0 through I/O15） are placed in a high impedance state when the device is deselected （CE HIGH）， the outputs are disabled （OE HIGH）， the BHE and BLE are disabled （BHE， BLE HIGH）， or during a write operation （CE LOW and WE LOW）。 The CY7C10612DV33 is available in a 54-pin TSOP II package with center power and ground （revolutionary） pinout. For a complete list of related documentation， click here.