The AD5362/AD5363 contain eight 16-/14-bit DACs in a single 52-lead LQFP package or 56-lead LFCSP package. The devices provide buffered voltage outputs with a span of 4× the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility， the device is divided into two groups of four DACs， and the output range of each group can be independently adjusted by an offset DAC. The AD5362/AD5363 offer guaranteed operation over a wide supply range with VSS from ?16.5 V to ?4.5 V and VDD from 8 V to 16.5 V. The output amplifier headroom requirement is 1.4 V， operating with a load current of 1 mA. The AD5362/AD5363 have a high speed 4-wire serial interface that is compatible with SPI， QSPI?， MICROWIRE?， and DSP interface standards and can handle clock speeds of up to 50 MHz. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register. Each DAC output is gained and buffered on chip with respect to an external SIGGNDx input. The DAC outputs can also be switched to SIGGNDx via the CLR pin.