ABSTRACT

　　The TPA2051D3 audio subsystem from TI uses the I 2C bus to communicate between integrated circuits in a system. This document explains how to choose the appropriate resistor values for the I 2C interface connection to the TPA2051D3.

　　Overview The TPA2051D3 uses the I 2C bus to communicate between integrated circuits in a system. It operates as an I 2C slave and employs two signals： SDA （data） and SCL （clock）。 The I 2C pins feature an open-drain architecture; therefore， an external pull-up resistor must be used for the SDA and SCL signals to set the logic high level for the bus. Figure 1 shows a typical application circuit with the TPA2051D3 and the host processor. VIO corresponds to the I 2C bus level， which can range from 1.7 V to 3.3 V

　　The TPA2051D3 holds the SDA pin low to indicate acknowledgement at each transfer operation. VOL corresponds to the voltage level at the SDA pin during the ACK clock period. By design， the expected VOLMax with a 3.3-mA sink current is VOLMax = 0.2●VIO.