Advance Information
MPC106 PCI Bridge/Memory Controller
Technical Summary
This document provides an overview of the MPC106 PCI bridge/memory controller
(PCIB/MC). It includes the following:
? An overview of MPC106 features
? Details about the MPC106 device. This includes descriptions of the MPC106’s
functional units and power management support.
? A description of the MPC106’s signals
? A description of the MPC106’s address maps and registers
In this document, the term ‘60x’ is used to denote a 32-bit microprocessor from the
PowerPC architecture family that conforms to the bus interface of the PowerPC 601?,
PowerPC 603?, or PowerPC 604? microprocessors. Note that this does not include the
PowerPC 602? microprocessor which has a multiplexed address/data bus. 60x processors
implement the PowerPC architecture as it is specified for 32-bit addressing, which provides
32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and floatingpoint
data types of 32 and 64 bits (single-precision and double-precision).