Two to Tango： MCUs Team Up with FPGAs

　　嵌入式設(shè)計(jì)人員花了大量的時(shí)間來尋找合適的微控制器（MCU）來完成手頭的任務(wù)。通常，空間是一個(gè)約束，原始性能、I/O、內(nèi)存資源、電源繪制和外圍設(shè)備的正確組合成為尋找合適配置的圣杯。

　　如果你有特定設(shè)計(jì)需要的專業(yè)邏輯，搜索會(huì)變得更加復(fù)雜。也許這是一個(gè)“秘密醬”，你的公司知道如何比別人做得更好，使最終產(chǎn)品脫穎而出。在這種情況下，沒有人能完全按照你想要的方式來制造一個(gè)微控制器。

　　還有另一種選擇：協(xié)同MCU和FPGA配對(duì)。高密度FPGA可以吸收，他們可以結(jié)合微太多邏輯，甚至房子MICROS，單獨(dú)做超過部分。此外，你的邏輯的專有本質(zhì)隱藏在FPGA內(nèi)部的窺探中。

　　本文討論了幾種允許設(shè)計(jì)者將FPGA技術(shù)與嵌入式處理器相結(jié)合的選項(xiàng)。我們將研究單片方法、片上系統(tǒng)（SOC）解決方案、堆棧和模塊。

　　Single-chip solutions

　　Micros can be made to run pretty fast. We are all familiar with multi-gigahertz processors at our fingertips. However， faster processors are typically more costly and harder to implement; PCB traces become transmission lines and tight impedance control is needed， especially on critical path signals. Not every design can shoulder the cost and time to develop with such devices.

　　This leaves lower cost， more general-purpose processors running at slower speeds as an alternative， more-economical choice for our designs. For non-demanding applications， this alone is good， but when the need for speed exceeds the micro’s cycle time， we have to make a choice. Software-based approaches cannot compete with the speed of a hard-logic implementation of a function. You can use discrete logic on a board， or couple the processor core with a pure logic resource like an FPGA.