1.0 INTRODUCTION .................................................................... 3
1.1 Interface Suggestions .................................................................... 1
1.2 Top 6 Issues .................................................................... 1
2.0 CPU INTERFACE MODES .................................................................... 1
3.0 CLOCKING STRUCTURE .....................................................................1
4.0 INTERFACING SCHEMATICS FOR MODE 3 ASYNCHRONOUS ................. 2
5.0 PAL DESCRIPTION .................................................................... 3
5.1 The CLK2 and PH1 Signals .....................................................................4
5.2 The Interrupt Signal to the Intel386TM Microprocessor .................................................................... 4
5.3 The Intel386TM Microprocessor W/RY Signal .................................................................... 4
5.4 The READYY Signal .............................................. 4
5.5 The CSY Signal to the 82527 .................................................................... 4
6.0 TIMING CONSIDERATIONS .................................................................... 6
6.1 Read Cycles .................................................................... 6
6.2 Write Timings .................................................................... 8
7.0 C-PROGRAM FOR INITIALIZING THE 82527 ............................................................... 9