本文介紹了一種應(yīng)用FPGA 器件完成高速數(shù)字傳輸?shù)姆椒ǎ眠@種方法實現(xiàn)無線收發(fā)芯片nRF2401A 的高速數(shù)據(jù)接口。為進(jìn)一步提高信息的傳輸速率，這里還對待傳輸?shù)臄?shù)據(jù)進(jìn)行了壓縮處理。涉及的高速數(shù)據(jù)接口和壓縮處理算法都用VHDL 實現(xiàn)，并通過實際
測試。
關(guān)鍵詞: 現(xiàn)場可編程陣列 數(shù)字傳輸 數(shù)字壓縮 數(shù)字無線電
Abstract：A high speed data transmission method based on FPGA is introduced and employed to realize the high speed data interface of wireless transceiver chip (nRF2401A). To further improve the transmission rate, the transmitted data is also compressed in the designed interface system. The high speed data interface and the corresponding data compressing algorithm are programmed using VHDL. The whole system has been tested, which shows the feasibility of the designing method based on FPGA.
Keywords： FPGA , digital transmission, digital compression, digital radio