文中重點闡述了用VerilogHDL 語言對USB2.0 協(xié)議層關(guān)鍵模塊的RTL 級設計和驗證
工作，并在XILINX ISE 軟件平臺上進行了FPGA 綜合。通過在ModelSim6.1 上仿真和ISE7.1上綜合結(jié)果表明本文設計的USB 協(xié)議層模塊是正確的。
關(guān)鍵詞：FPGA，通用串行總線，VerilogHDL，協(xié)議層，RTL
Design and verification of USB protocol layer based on FPGA
YIN Baqun ZHOU Xianzhong
（Department of Control and Systems Engineering, Nanjing University, Nanjing, 210093）
Abstract As the main part of the paper, the design and verification of USB protocol layer key
modules are described in detail. Modules of USB2.0 protocol layer controller are designed in RTL by using VerilogHDL, and synthesized on the ISE platform of XILINX. The validity of the
modules of USB protocol layer is approved by simulation and synthesis.
Keyword FPGA, Universal Serial Bus, VerilogHDL, Protocol Layer, RTL