SAR開(kāi)關(guān)時(shí)序的非二進(jìn)制結(jié)構(gòu)

　　I. INTRODUCTION

　　Atrendin receiver design for digital TV， satellite receivers， and set-top boxes is the move towards software-defined radios， where the embedded analog-to-digital converter （ADC） is moved closer to the antenna. Such ADCs require 8–10 bits of resolution， a large bandwidth to enable subsampling/down-conversion， and limited power consumption of a few hundred milliwatts to be able to embed the ADC with the digital baseband processing in a single IC. The time-interleaved ADC architecture shown in Fig. 1 offers the combination of good power efficiency with high speed ［2］， ［5］， ［6］。 Key aspects are high-speed sampling， excellent matching between channels， and power efficiency of the complete system. This paper extends the results presented in ［5］ and ［9］ with in-depth analysis and the presentation of an improved design. This paper is organized as follows. First， the time-interleaved track-and-hold （T&H） is discussed in Section II， with channel matching issues between the T&H channels in Section III. Second， the sub-ADC architecture is presented in Section IV， Manuscript received August 24， 2007; revised November 4， 2007. S. M. Louwsma， A. J. M. van Tuijl， and B. Nauta are with the IC Design Group， CTIT Research Institute， University of Twente， 7500 AE Enschede， The Netherlands （e-mail： S.M.Louwsma@alumnus.utwente.nl）。 M. Vertregt is with NXP Semiconductors， High Tech Campus WY2， 5656 AE Eindhoven， The Netherlands. Digital Object Identifier 10.1109/JSSC.2008.917427 Fig. followed by calibration aspects and measurement results in sections V and VI. The paper ends with the presentation of an improved design and its performance in Section VII and conclusions in Section VIII.