The MMA52xxLW family， a SafeAssure solution， includes the AKLV27 and PSI5 Version 1.3 compatible overdamped X-axis satellite accelerometers.

　　The Factory programmed OTP array is verified for errors with a 3-bit CRC. The CRC verification is enabled only when the factory programmed array is locked. The CRC verification uses a generator polynomial of g（x） = X3 + X + 1， with a seed value = ‘111’。 Once the CRC verification is enabled， the CRC is continuously calculated on all bits in registers $00， $01， $02， $03， and $04 and on the factory programmable device configuration bits with the exception of the factory lock bit. Bits are fed in from right to left （LSB first）， and top to bottom （lower addresses first） in the register map. The calculated CRC is then compared against the stored 3 bit CRC. If a CRC error is detected in the OTP array， the IDEF_B bit is cleared in the SC register. The CRC verification is completed on the memory registers which hold a copy of the fuse array values， not the fuse array values.